The present invention relates to analog memory elements, and more specifically, to a mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit (RPU).
Many computer-implemented applications are computationally intensive and require parallel processing. For example, in machine learning or supervised learning, deep neural network (DNN) training techniques require memory calls that can add up over billions of cycles and, thus, benefit from fast memory access. RPUs are arrays of memory elements that combine processing and non-volatile memory and can fetch data as fast as it is processed at lower voltages compared to more traditional non-volatile memory (NVM) devices.